Assigned reading

Note: These articles are copyrighted so I have restricted access to students in the class. Email me if you need access.

• A. Keshavarzi, “Technology Scaling and Low-Power Circuit Design,” in The VLSI Handbook, W.-K. Chen, Ed. CRC Press, 2006.
• L. Shang and R. P. Dick, “Thermal Crisis: Challenges and Potential Solutions,” in IEEE Potentials, pp. 31–35, vol. 25, no. 5, Sep. 2006. Notes: Introduction of thermal problems in computing.
• G. Chen, R. Yang, and X. Chen, “Nanoscale Heat Transfer and Thermal-Electric Energy Conversion,” in J. Phys. IV France, vol. 125, 2005.
• D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” in Proc. Int. Symp. Computer Architecture, Jun. 2000.
• V. Tiwari, S. Malik, and A. Wolfe, “Power Analysis of Embedded Software: a First Step Towards Software Power Minimization,” in IEEE Trans. VLSI Systems, Dec. 1994.
• D. Brooks, R. P. Dick, R. Joseph, and L. Shang, “Power, thermal, and Reliability Modeling in Nanometer-Scale Microprocessors,” to appear in IEEE Micro.
• R. Joseph, D. Brooks, and M. Martonosi, “Control Techniques to Eliminate Voltage Emergencies in High Performance Processors,” in Proc. Int. Symp. High-Performance Computer Architecture, pp. 79–90, Feb. 2003.
• P. Pillai, and K. G. Shin, “Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems,” Proc. ACM Symp. Operating Systems Principles, pp. 89–102, Dec. 2001.
• K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperature-Aware Microarchitecture,” in Proc. Int. Symp. Computer Architecture, pp. 2–13, Jun. 2003.
• Y. Liu, R. P. Dick, L. Shang, and H. Yang, “Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation is Easy,” in Proc. Conf. on Design, Automation, and Test in Europe, pp. 204–209, March 2007.
• J. Cong, J. Wei, and Y. Zhang, “A Thermal-Driven Floorplanning Algorithm for 3D ICs,” in Proc. Int. Conf. Computer-Aided Design, pp. 306&endash;313, Nov. 2004.
• R. Mukherjee and S. O. Memik, “An Integrated Approach to Thermal Management in High-Level Synthesis,” in IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 11, Nov. 2006.
• J. Long, R. Mukherjee, S. O. Memik, and G. Memik, “Thermal Monitoring Mechanisms for Chip Multiprocessors,” under review.
• B. Goplen and S. Sapatnekar, “Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach,” in Proc. Int. Conf. Computer Aided Design, Nov. 2003.
• D. Brooks and M. Martonosi, “Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance,” in Proc. Int. Symp. High-Performance Computer Architecture, Jan. 1999.
• Y. Wang, H. Luo, K. He, R. Luo, H. Yang, and Y. Xie, “Temperature-Aware NBTI Modeling and the Impact of Input Vector Control on Performance Degradation,” in Proc. Conf. on Design, Automation, and Test in Europe, Mar. 2007.
• E. Humenay, D. Tarjan, and K. Skadron, “The Impact of Systematic Process Variations on Symmetrical Performance in Chip Multi-processors,” in Proc. Conf. on Design, Automation and Test in Europe, pp. 53&endash;58, Apr. 2007.
• A. Dasdan and I. Hom, “Handling Inverted Temperature Dependence in Static Timing Analysis,” in ACM Trans. Design Automation of Electronic Systems, pp. 306&endash;324, Vol. 11, No. 2, Apr. 2006.
• E.-Y. Chung, L. Benini, A. Bogliolo, Y.-H. Lu, and G. De Micheli, “Dynamic Power Management for Nonstationary Service Requests,” in IEEE Trans. on Computers, Vol. 31, No. 11, Nov. 2002.

References

• W. Strunk Jr. and E. B. White, The Elements of Style, Macmillan Publishing Co., Inc., 2000.
• International Technology Roadmap for Semiconductors
• J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, “Exploiting Structural Duplication for Lifetime Reliability Enhancement,” in Proc. Int. Symp. Computer Architecture, Jun. 2005.
• Y. Yang, Z. P. Gu, R. P. Dick, and L. Shang, “ISAC: Integrated Space and Time Adaptive Chip-Package Thermal Analysis,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Jan. 2007.
• Y. Yang, C. Zhu, Z. P. Gu, L. Shang, and R. P. Dick, “Adaptive Multi-Domain Thermal Modeling and Analysis for Integrated Circuit Synthesis and Design,” in Proc. Int. Conf. Computer-Aided Design, Nov. 2006.
• P. Rosinger, B. M. Al-Hashimi and K. Chakrabarty, “Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 2502–2512, Nov. 2006.
• E. Pop, R. Dutton, and K. Goodson, “Detailed Heat Generation Simulations via the Monte Carlo Method,” in Int. Conf. Proc. Simulation of Semiconductor Processes and Devices, Sep. 2003.
• R. Kumar and V. Kursun, “Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS circuits,” in IEEE Trans. Circuits and Systems–II Express Briefs, Vol. 53, No. 10, Oct. 2006.
• B. G. Streetman, Solid State Electronic Devices, Prentice Hall, any recent edition.
• A. Raghunathan, N. K. Jha, and S. Dey, High-level Power Analysis and Optimization, Kluwer Academic Publishers, 1997.
• T.-Y. Wang, Y.-M. Lee, and C. C.-P. Chen, “3D Thermal-ADI – An Efficient Chip-Level Transient Thermal Simulator,” in Proc. Int. Symp. Physical Design, Apr. 2003.
• Yung-Hsiang Lu, Luca Benini, and Giovanni De Micheli, “Operating-system directed power reduction,” in Prof. Int. Symp. on Low Power Electronics and Design, Aug. 2000.
• Tao Li and Lizy Kurian John, “Operating System Directed Power Minimization Through Run-Time Processor Resource Adaptation,” in Microprocessors and Microsystems, vol. 30, 2006.

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