The Workshop on Compiler-Assisted System-On-Chip Assembly gives researchers working on compilation and synthesis of systems-on-chip a venue to learn about the work of their peers and discuss ongoing research in detail.
Please click talk topics to see abstracts and biographical sketches.
| Time | Topic | Speaker |
|---|---|---|
| 8:45–9:00 | Welcome | CASA Organizers |
| 9:00–9:30 | OpenMP Compilation for Stacked-DRAM MPSoC Architectures: NUMA Revisited | Luca
Benini University of Bologna |
| 9:30–10:00 | Tools for Optimization of Active Cooling Systems for MPSoCs | Seda Öğrenci Memik Northwestern University |
| 10:00–10:30 | Break | |
| 10:30–11:00 | Customizing Memories for MPSoCs | Sudeep
Pasricha Colorado State University |
| 11:00–11:30 | Cost-Effective Lifetime Improvement for NoC-Based MPSoCs | Brett Meyer Carnegie–Mellon University |
| 11:30–12:00 | Heterogeneous Multi-Processor Pipelines: an MPSoC Story | Sridevan Parameswaran University of New South Wales |
| 12:30–14:00 | Lunch | |
| 14:00–14:30 | ESL Synthesis Across Hardware/Software Boundaries | Christian
Haubelt Universität Erlangen–Nürnberg |
| 14:30–15:00 | A Decade of Compiler Driven Customization: Retrospects and Prospects | Krishna
V. Palem Rice University |
| 15:00–15:30 | Optical Network-on-Chip and Optical Router | Jiang Xu Hong Kong University of Science and Technology |
| 15:30–16:00 | Cyber-Physical Energy Systems: SOC Architectures for Aggressively Duty-Cycled Systems | Rajesh Gupta,
University of California San Diego |
| 16:00–16:30 | Break | |
| 16:30–17:45 | Panel — Separating the Wheat from the Chaff: What Are the Fundamental New Scientific Problems in the Synthesis of Cyber-Physical Systems? | Moderator: Daniel
Gajski Panelists: Luca Benini, Naehyuck Chang, Nikil Dutt, and Rajesh Gupta |
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