Abstract for Customizing Memories for MPSoCs

Memory architectures are a critical factor influencing performance and power dissipation in Multi-Processor Systems-on-Chip (MPSoCs). There is strong experimental evidence to suggest that the customization of the memory architecture and optimizations must be tightly coupled with other design decisions to improve memory bandwidth and latency, and reduce power dissipation. This talk will focus on two directions pertaining to memory customization for MPSoCs. The first part of the talk will present a unified methodology for uncovering parallelism in multimedia applications and efficiently mapping tasks and data in MPSoC environments. The second part of the talk will present a framework for co-synthesis of memory and on-chip communication architectures in MPSoCs. The premise of this work is the observation that the memory architecture drives most of the communication on a chip, and thus has a significant impact on how the on-chip communication fabric is designed.

Biographical Sketch for Sudeep Pasricha

Dr. Pasricha is an Assistant Professor in the Department of Electrical and Computer Engineering at Colorado State University. He received the B.E. degree in Electronics and Communication engineering from Delhi Institute of Technology, Delhi, India, in 2000, and his M.S. and Ph.D. degrees in Computer Science from the University of California, Irvine in 2005 and 2008, respectively. Dr. Pasricha is a TPC member of the CODES+ISSS, ISQED, NOCS and VLSI Design conferences, and also involved in the committees for the SIGDA DAC PhD Forum and ICCAD CADathalon. His current research interests are in the areas of networks-on-chip (NoC) and emerging interconnect technologies (photonic, carbon nanotube, 3D), memory architecture synthesis, fault-tolerant computing, system-level modeling languages and design methodologies for embedded systems, computer architecture, and VLSI CAD.