Project deadlines and template documents

• 20 October: Mini-project report.
• 25 October: Main project selection.
• Due date for main project presentation to be announced.
• 13 December: Main project report.
• Template mini-project proposal.
• Template mini-project proposal source.
• Template mini-project proposal bibtex database.

Example projects for EECS 598: Embedded System Design and Synthesis

A number of projects started in previous offerings of the course have later been published in research conferences and journals.

• L. Yang, R. P. Dick, H. Lekatsas, and S. Chakradhar, “High-performance operating system controlled on-line memory compression,” in ACM Trans. Embedded Computing Systems, to appear. Notes: New compression algorithm doubles usable embedded system memory without hardware or application changes and with negligible performance and power overhead. NEC uses this technology in their cellphones.
• S. Yazji, X. Chen, R. P. Dick, and P. Scheuermann, “Implicit user re-authentication for mobile devices,” in Proc. Int. Conf. on Ubiquitous Intelligence and Computing, Jul. 2009.
• L. Bai, H. Lekatsas, and R. P. Dick, “Adaptive filesystem compression for embedded systems,” in Proc. Design, Automation, and Test in Europe Conf., Mar. 2008. Notes: Technique to increase usable storage on embedded systems. Improves performance by 67% compared to currently-used technique: uniform compression. 24% acceptance rate for conference.
• S. Kim, R. P. Dick, and R. Joseph, “Power Deregulation: Eliminating Off-Chip Voltage Regulation Circuitry From Embedded Systems,” in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, pp. 105–110, Oct. 2007. Notes: Technique to eliminate power regulation hardware from embedded chip multiprocessors.
• S. Jevtic, M. Kotowsky, R. P. Dick, P. A. Dinda, and C. Dowding, “Lucid Dreaming: Reliable Analog Event Detection for Energy-Constrained Applications,” in Proc. Int. Symp. Information Processing in Sensor Networks, pp. 350–359, Apr. 2007. Notes: Ultra-low-power event detection sensor interface technology permits 250× reduction in power consumption for event-driven applications such as structural integrity monitoring of buildings and bridges.
• D. Zaretsky, G. Mittal, R. P. Dick, and P. Banerjee, “Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs,” in Proc. Int. Symp. Quality Electronic Design, pp. 595–601, March 2007. Notes: Techniques to reduce critical timing paths during FPGA synthesis.
• A.-H. Liu and R. P. Dick, “Automatic Run-Time Extraction of Communication Graphs From Multithreaded Applications,” in Proc. Int. Conf. Hardware/Software Codesign and System Synthesis, pp. 46–51, Oct. 2006. Notes: Simulator module dynamically determines communication patterns of arbitrary multi-threaded Linux applications for use in embedded system synthesis.

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