These are the topics we covered in the course. I start from this list when
figuring out what questions to ask. I need to pick a subset, though, because
otherwise the exam would take too long.

-Robert Dick-

----
logic minimization
  two-level vs. multi-level logic
    advantages/disadvantages
  don't-cares
    definitions, finding
  manual equivalence proofs
  Karnaugh Maps
    SOP and POS
  Quine-McCluskey
    don't-cares
  NP-Completeness
    meaning
  Espresso
    moves
    find cubes
      relatively essential
      partially redundant
      totally redundant cubes
  kernel extraction
    method
    advantages/disadvantages
implementation technologies
  CMOS transistors
    why AND and OR are hard
    the switch to high-k
  transmission gates
  multiplexors
  demultiplexors
  PALs, PLAs
  ROMs
  non-volatile memory
    how floating gates work
  technology mapping
    slow optimal algorithm for DAGs
    fast optimal algorithm for trees
    fast near-optimal algorithm for DAGs
  FPGAs and other PLDs
    basic knowledge of architecture
  low-power design
timing
  timing models
  delay analysis
    topological sort
    slack
    critical path
  Schmitt triggers
  hazards
    dynamic and static
arithmetic
  number systems
  adders
  multipliers
  understand the concept of ALUs
sequential elements
  latches
  flip-flops
  RS, D, etc.
  be able to build latches and flip-flops from other devices
  be able to build other devices from latches and flip-flops
FSM design
  regular expressions
  NFAs
  DFAs
  state minimization of fully specified FSMs
  state minimization of FSMs with don't-cares
  heuristic state assignment
  multi-output FSM design
  AFSM design considerations
design languages
  basic familiarity with all main classes of system design languages
  ability to understand simple combinational and sequential VHDL
  what are perl and python?
covering problems
  where do they appear
  how to manually solve them
  how difficult are they
  why are they difficult
process scaling impact on
  wiring
  globally synchronous systems
testing
  purpose of testing
  excitation and sensitization
  the D Algorithm
  the concept of unrolling sequential circuits to permit the use of
    combinational test generation on sequential circuits
understand all labs