Thermal Modeling, Management, and Optimization for High-Performance Integrated Circuit Testing

Increasing circuit integration and power densities pose serious challenges while testing system-on-chip (SoC) and network-on- chip (NoC) integrated circuits (ICs). It is known that the maximum power consumption during testing is frequently several times higher than that during normal operation. High IC power consumption plus limited cooling support increases IC temperature, inducing damage and invalidating test results due to changes in path delay. Increasing process variation, and its impact on IC temperature, power consumption, and performance, further exacerbate the testing challenge. It is important to systematically consider thermal issues during the generation of test sequences and schedules, as well as during test application.

Our first work developes a optimal formulation the minimal-duration tmeperature-constrained test scheduling for MPSoCs (Multi-Processor Systems-on-Chip). Our results improve on the test schedule time of the best existing algorithm by 10.8% on average. We also develop an effecient heuristic that gnerally produces the same results as the optimal algorithm, while requiring little CPU time, even for large problem instances.


Active Participants

  • Niraj Jha, PI at Princeton University
  • Robert Dick, co-PI at the University of Michigan
  • Li Shang, co-PI at the University of Colorado at Boulder
  • David Bild, Ph.D. student at the University of Michigan
  • Muzaffer Simsir, Ph.D. student at Princeton University
  • Former Participants

  • Xiaobo Sharon Hu, Professor at Universtiy of Notre Dame
  • Alok Choudhary, Professor at Northwestern University
  • Tam Chantem, Ph.D. student at University of Notre Dame
  • Sanchit Misra, Ph.D. student at Northwestern University
  • Prabhat Kumar, Ph.D. student at Northwestern University,
  • Talks

  • Temperature-Aware Test Scheduling for Multiprocessor Systems-On-Chip, David Bild, ICCAD 2008 (pdf)
  • Temperature-Aware Test Scheduling for Multiprocessor Systems-On-Chip, David Bild, Intel Corp., Nov. 2008
  • Papers

  • D. R. Bild, S. Misra, T. Chantem, P. Kumar, R. P. Dick, X. S. Hu, L. Shang, and A. Choudhary, Temperature-Aware Test Scheduling For Multiprocessor Systems-On-Chip, in Proc. Int. Conf. Computer-Aided Design (ICCAD 2008), November 2008, pp. 59-66. pdf
  • Acknowledgements

    This project is made possible by support from the Semiconductor Research Corporation (SRC) under grant 2007-TJ-1589 and the National Science Foundatation (NSF) under grants CCF-0702761, CNS-0347941, CNS-0410771, CNS-0404341, IIS-0536994, and CCF-0444405.