| University of Michigan |
|---|
| Electrical Engineering and Computer Science |
| Mr. Yun Xiang |
| Prof. Robert Dick |
Integrated circuit (IC) reliability is important. As a result of IC process technology scaling, IC power density increases. This tends to increase temperature and current density, each of which strongly influence lifetime fault processes such as electromigration, time-dependent dielectric breakdown, stress migration, and negative bias temperature instability. As a result of scaling from a 180 nm to 65 nm process technology, temperature generally increases by 14 degrees. It is reported that a 10-15 degrees increase in temperature halves IC lifetime as a result of increased wear due to lifetime fault processes.
ICs are composed of many devices, e.g., wires and transistors. Without reliability enhancement technologies, a fault in any device can cause the functional unit composed of devices to fail. Considering reliability during system-level IC design has the potential to yield greater improvements to lifetime at lower costs than considering only device-level reliability enhancement techniques. System-level changes to floorplan or power state control can impact the temperatures and current densities of thousands of devices. It would be impractical to develop circuits to compensate for the failure of each individual transistor, but system-level redundancy of functional components containing many devices is commonly used in modern ICs.
This is a system-level reliability modeling software based on the device level failure models. This software has improved reliability estimation accuracy compared to the previous models. At component level it uses direct calculation and at system level it uses Monte-Carlo simulation. It also take into account of both intra-die and inter-die process variation. This tool also provide differnt system-level criteria for static and dynamic optimizations. The current release includes the ISAC2 thermal analysis tool.
Page maintained by Yun Xiang.