This project focuses on the development of circuit level techniques to reduce Negative Bias Temperature Instability (NBTI) induced fatigue.
NBTI is a significant reliability conern for nanoscale CMOS circuits which manifests itself as an increase in thershold voltage that reduces switching speed. At the atomic level, NBTI is caused by an electric field dependent disassociation of Si-H bonds at the Si-SiO2 interface. The freed hydrogen diffuses into the oxide, resulting in interface traps that increases the threshold voltage. This disassociation is most prevalent for PMOSFETs under negative bias (Vgs = -Vdd). When the stress is removed (Vgs = 0), the diffusions reverses and some of the hydrogen can rebond with the Si, removing the interface traps. This reversal is called the recovery effect.
To date we have looked at two methods for managing and mitigating NBTI.
The first involves increasing the operating voltage (Vdd) to compensate for the decrease in switching speed due to NBTI. Because the NBTI degradation rate increases with operating voltage, if the higher voltage is applied early in the circuit's lifetime, it has the effect of further increasing the degradation. Instead, we propose scheduled voltage scaling, a technique which gradually increases the operating voltage to ensure operating speed while minimizing NBTI degradation.
The second looks at reducing NBTI degradation in idle function units. To reduce power consumption, idle function units are often clock-gated resulting in static inputs to the underlying transistors. For transistors with low inputs, this can result in significant NBTI degradation. We propose the use of input vector control and internal node control to minimize the total impact on critical path delay. By controlling the input state of the transistors in the functional unit, NBTI stress on critical transistors can be removed, resulting in an approximate 27% decrease in NBTI induced delay.